1. Field of the Invention
The invention relates generally to a method of fabricating a high-voltage high-power integrated circuit device, and more particularly to a method of fabricating a high-voltage high-power integrated circuit device using a trench isolation technology capable of significantly reducing the isolated area for electrically isolating a logic CMOS device as well as the high-voltage high-power device and easily controlling the impurity concentration of a deep well.
2. Description of the Prior Art
Generally, a MOS device in which loss of the driving circuit is low is more used than the bipolar transistor as the power device used in the high-voltage high-power integrated circuit (IC). A DMOS is mainly used as the high power device, which includes LDMOS (lateral DMOS) and VDMOS (vertical DMOS). When the power integrated circuit device is fabricated, there are advantages that the process can be simplified and the driving power of the VDMOS transistor become larger, but there is a difficulty in fabricating an integrated circuit (IC) rather than the LDMOS transistor, if a SOI (silicon-on-insulator) substrate is used rather than using a bulk silicon substrate. Therefore, the SOI substrate and the LDMOS transistor are usually used in fabricating the high-voltage high-power integrated circuit (IC).
The high voltage LDMOS transistor and the logic CMOS device are electrically isolated by a device isolation film, which is formed by the trench isolation technology. The trench isolation technology has advantages that it can significantly reduce the isolation area rather than using a p-n junction, significantly reduce the parasitic capacitance and electrically isolate the device even at a high voltage.
The high-voltage high-power integrated circuit (IC) using the SOI substrate consists of a high voltage n-LDMOS transistor and a high voltage p-LDMOS transistor, and a logic CMOS device, as shown in FIG. 1. P type impurities (B, BF2) and n type impurities (P, As) are implanted into regions where a deep p-well (or deep n-well) will be formed, respectively, and an annealing process is performed at high temperature for a long period of time to diffuse the impurities, thus forming the deep p-well 2 (or deep n-well 3). Then, p type impurities (B, BF2) and n type impurities (P, As) are implanted into regions where a p-well and a n-well will be formed, respectively, and an annealing process is performed at high temperature to form the p-well 4 and the n-well 5. After the deep p-well 2 (or deep n-well 3), the p-well 4 and the n-well 5 are formed, the silicon layers 2 and 3 are etched up to the SOI interlayer oxide film 30 to form a trench in order to isolate various components at the silicon substrate 1 and the silicon layers 2 and 3 on the SOI interlayer oxide film 30. Next, silicon within the trench is thermally oxidized to grow the oxide film 33. Thereafter, an oxide film 33 is deposited by means of chemical vapor deposition(CVD) method, and the like and polysilicon 21 into which an impurity is not introduced is deposited by means of chemical vapor deposition method, or the like. Then, polysilicon 21 except for an oxide film 33 which is grown within the trench and the oxide film 33 on the surface is removed by means of etch-back using the photoresist film or chemical mechanical polishing (CMP) method to isolate the device within the trench. In this case, if the deep wells 2 and 3 are formed before the trench is formed, the impurity at an edge of the deep wells 2 and 3 is diffused toward the lateral direction as well as the depth direction during the annealing process at high temperature. Due to this, the concentration of the impurity at the edge of the deep wells 2 and 3 becomes lower than the center of the wells. As a result, it is required that the high voltage device and the logic CMOS device are electrically isolated by two-line trench isolation, by forming a trench within a region where the concentration of the impurity is not lowered at the well edge and also forming a trench outside the wells 2 and 3 in order to completely isolate other high voltage devices.
As such, the conventional technology has disadvantages that it requires the two-line isolation of the trench in order to completely solve a problem depending on the lateral diffusion of the impurity and that the area necessary to isolate the devices is significantly increased.